Spartan-3 FPGA Family Integrated Circuit Chip Complete Data Sheet XC3S400-4PQG208C

 
Spartan™-3 FPGA Family: Complete Data Sheet
 
Features
• Very low cost, high-performance logic solution for high-volume, consumer-oriented applications
  - Densities as high as 74,880 logic cells
  - Three power rails: for core (1.2V), I/Os (1.2V to 3.3V), and auxiliary purposes (2.5V)
• SelectIO™ signaling
  - Up to 784 I/O pins
  - 622 Mb/s data transfer rate per I/O
  - 18 single-ended signal standards
  - 6 differential I/O standards including LVDS, RSDS
  - Termination by Digitally Controlled Impedance
  - Signal swing ranging from 1.14V to 3.45V
  - Double Data Rate (DDR) support
• Logic resources
  - Abundant logic cells with shift register capability
  - Wide multiplexers
  - Fast look-ahead carry logic
  - Dedicated 18 x 18 multipliers
  - JTAG logic compatible with IEEE 1149.1/1532
• SelectRAM™ hierarchical memory
  - Up to 1,872 Kbits of total block RAM
  - Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
  - Clock skew elimination
  - Frequency synthesis
  - High resolution phase shifting
• Eight global clock lines and abundant routing
• Fully supported by Xilinx ISE development system
  - Synthesis, mapping, placement and routing
• MicroBlaze™ processor, PCI, and other cores
• Pb-free packaging options
• Low-power Spartan-3L Family and Automotive Spartan-3 XA Family options
 
DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows:
 
Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other families. Values are subject to change. Use as estimates, not for production.
 
Preliminary: Based on characterization. Further changes are not expected.
 
Production: These specifications are approved once the silicon has been characterized over numerous production lots. Parameter values are considered stable with no future changes expected.
 
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following applies unless otherwise noted: The parameter values published in this module apply to all Spartan™-3 devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades. All parameters representing voltages are measured with respect to GND.
 
Some specifications list different values for one or more die revisions. All presently available Spartan-3 devices are classified as revision 0. Future updates to this module will introduce further die revisions as needed.
 
If a particular Spartan-3 FPGA differs in functional behavior or electrical characteristic from this data sheet, those differences are described in a separate errata document. The errata documents for Spartan-3 FPGAs are living documents and are available online.
 
All specifications in this module also apply to the Spartan-3L family (the low-power version of the Spartan-3 family). Refer to the Spartan-3L datasheet (DS313) for any differences.
 
Table 1: Absolute Maximum Ratings

Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
 
2. As a rule, the VIN limits apply to both the DC and AC components of signals. Simple application solutions are available that show how to handle overshoot/undershoot as well as achieve PCI compliance. Refer to the following application notes: "Virtex-II Pro™ and Spartan-3 3.3V PCI Reference Design" (XAPP653) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (XAPP659).
 
3. All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) draw power from the VCCO power rail of the associated bank. Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCO rail do not turn on. Table 5 specifies the VCCO range used to determine the max limit. When VCCO is at its maximum recommended operating level (3.45V), VIN max is 3.95V. The maximum voltage that avoids oxide stress is VINX = 4.05V. As long as the VIN max specification is met, oxide stress is not possible.
 
4. All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX rail do not turn on. Table 5 specifies the VCCAUX range used to determine the max limit. When VCCAUX is at its maximum recommended operating level (2.625V), VIN max < 3.125V. As long as the VIN max specification is met, oxide stress is not possible. For information concerning the use of 3.3V signals, see the 3.3V-Tolerant Configuration Interface section in Module 2: Functional Description.
 
5. For soldering guidelines, see "Device Packaging and Thermal Characteristics" at www.xilinx.com/bvdocs/userguides/ug112.pdf.