SN74LVC2T45DCUR Electronic IC Chip DUAL BIT DUAL SUPPLY BUS TRANSCEIVER

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SN74LVC2T45

DUAL BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS 

 

* Available in the Texas Instruments NanoStar^TM and NanoFree^TM Packages

* Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range

* V_CC Isolation Feature − If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State

* DIR Input Circuit Referenced to VCCA

* Low Power Consumption, 10-µA Max I_CC

* ±24-mA Output Drive at 3.3 V

* I_off Supports Partial-Power-Down Mode Operation

* Max Data Rates

   − 420 Mbps (3.3-V to 5-V Translation)

   − 210 Mbps (Translate to 3.3 V)

   − 140 Mbps (Translate to 2.5 V)

   − 75 Mbps (Translate to 1.8 V)

* Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

* ESD Protection Exceeds JESD 22

   − 2000-V Human-Body Model (A114-A)

   − 200-V Machine Model (A115-A)

   − 1000-V Charged-Device Model (C101)

description

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V_CCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input.

The SN74LVC2T45 is designed so that the DIR input circuit is supplied by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state. NanoStar^TM and NanoFree^TM package technology is a major breakthrough in IC packaging concepts, using the die as the package.

absolute maximum ratings over operating free-air temperature range

(unless otherwise noted)†

Supply voltage range, V_CCA and V_CCB  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−0.5 V to 6.5 V

Voltage range applied to any output in the high-impedance or power-off state, V_O

    (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

Voltage range applied to any output in the high or low state, V_O

    (see Notes 1 and 2):  A port  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_CCA + 0.5V

                                      B port  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_CCB + 0.5V

Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −50 mA

Output clamp current, I_OK (V_O < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA

Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA

Package thermal impedance, θ_JA (see Note 3): DCT package  . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W

                                                                          DCU package . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W

                                                                          YEP/YZP package  . . . . . . . . . . . . . . . . . . . . . 102°C/W

Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

logic diagram (positive logic)