IR2113S digital integrated circuits Integrated Circuit Chip HIGH AND LOW SIDE DRIVER
circuit board ic
,electronic components ic
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
HIGH AND LOW SIDE DRIVER
Features
• Floating channel designed for bootstrap operation
Fully operational to +500V or +600V
Tolerant to negative transient voltage
dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for both channels
• 3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground ±5V offset
• CMOS Schmitt-triggered inputs with pull-down
• Cycle by cycle edge-triggered shutdown logic
• Matched propagation delay for both channels
• Outputs in phase with inputs
Product Summary Packages
VOFFSET (IR2110) (IR2113) |
500V max. 600V max. |
IO+/- | 2A / 2A |
VOUT | 10 - 20V |
ton/off (typ.) | 120 & 94 ns |
Delay Matching (IR2110) (IR2113) |
10 ns max. 20ns max. |
Description
The IR2110/IR2113 are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol | Definition | Min. | Max. | Units | |
VB | High side floating supply voltage | (IR2110) | -0.3 | 525 | V |
(IR2113) | -0.3 | 625 | |||
VS | High side floating supply offset voltage | VB - 25 | VB + 0.3 | ||
VHO | High side floating output voltage | VS - 0.3 | VB + 0.3 | ||
VCC | Low side fixed supply voltage | -0.3 | 25 | ||
VLO | Low side output voltage | -0.3 | VCC + 0.3 | ||
VDD | Logic supply voltage | -0.3 | VSS + 25 | ||
VSS | Logic supply offset voltage | VCC - 25 | VCC + 0.3 | ||
VIN | Logic input voltage (HIN, LIN & SD) | VSS - 0.3 | VDD + 0.3 | ||
dVs/dt | Allowable offset supply voltage transient (figure 2) | - | 50 | V/ns | |
PD | Package power dissipation @ TA ≤ +25°C | (14 lead DIP) | - | 1.6 | W |
(16 lead SOIC) | - | 1.25 | |||
RTHJA | Thermal resistance, junction to ambient | (14 lead DIP) | - | 75 | °C/W |
(16 lead SOIC) | - | 100 | |||
TJ | Junction temperature | - | 150 | °C | |
TS | Storage temperature | -55 | 150 | ||
TL | Lead temperature (soldering, 10 seconds) | - | 300 |
Functional Block Diagram
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