SN74LV165ADR large scale integrated circuit Integrated Circuit Chip PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SN54LV165A, SN74LV165A

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

• 2-V to 5.5-V V_CC Operation
  
• Max t_pd of 10.5 ns at 5 V
  
• Support Mixed-Mode Voltage Operation on All Ports
• 
  I_off Supports Partial-Power-Down Mode Operation
  
• Latch-Up Performance Exceeds 250 mA Per JESD 17
  
• ESD Protection Exceeds JESD 22
  • − 2000-V Human-Body Model (A114-A)
  • − 200-V Machine Model (A115-A)
  • − 1000-V Charged-Device Model (C101)

SN54LV165A . . . J OR W PACKAGE SN74LV165A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)

SN74LV165A . . . RGY PACKAGE (TOP VIEW)

SN54LV165A . . . FK PACKAGE (TOP VIEW)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.5 V to 7 V

Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Voltage range applied to any output in the high-impedance

    or power-off state, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_CC + 0.5 V

Input clamp current, I_IK (V_I < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −20 mA

Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±25 mA

Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA

Package thermal impedance, θ_JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

                                                     (see Note 3): DB package  . . . . . . . . . . . . . . . . . . . . . . . . . . 82 °C/W

                                                     (see Note 3): DGV package  . . . . . . . . . . . . . . . . . . . . . . .  120 °C/W

                                                     (see Note 3): NS package  . . . . . . . . . . . . . . . . . . . . . . . . . . 67 °C/W

                                                     (see Note 3): PW package  . . . . . . . . . . . . . . . . . . . . . . . .  108 °C/W

                                                     (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . .  39 °C/W

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  −65 °C to 150°C

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5.

logic diagram (positive logic)

typical shift, load, and inhibit sequences

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