HEF4027BP,652 Original Integrated Circuit chip in electronics Integrated Circuit Chip Dual JK flip-flop
electronics ic chip
,integrated circuit ic
HEF4027B
Dual JK flip-flop
General description
The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
Features
■ Fully static operation
■ 5 V, 10 V, and 15 V parametric ratings
■ Standardized symmetrical output characteristics
■ Operates across the full industrial temperature range −40 °C to +85 °C
■ Complies with JEDEC standard JESD 13-B
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
Applications
■ Registers
■ Counters
■ Control circuits
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
| Symbol | Parameter | Conditions | Min | Max | Unit |
| VDD | supply voltage | −0.5 | +18 | V | |
| IIK | input clamping current | VI < 0.5 V or VI > VDD + 0.5 V | - | ±10 | mA |
| VI | input voltage | −0.5 | VDD + 0.5 | V | |
| IOK | output clamping current | VO < 0.5 V or VO > VDD + 0.5 V | - | ±10 | mA |
| II/O | input/output current | - | ±10 | mA | |
| IDD | supply current | - | 50 | mA | |
| Tstg | storage temperature | −65 | +150 | °C | |
| Tamb | ambient temperature | in free air | -40 | +80 | °C |
| Ptot | total power dissipation | Tamb −40 °C to +125 °C | |||
| DIP16 package [1] | - | 750 | mW | ||
| SO16 package [2] | - | 500 | mW | ||
| P | power dissipation | per output | - | 100 | mW |
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
Functional diagram
Logic diagram of one flip-flop
Pin configuration
Stock Offer (Hot Sell)
| Part NO. | Q'ty | MFG | D/C | Package |
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| PIC12F675-I/SN | 3630 | MICROCHIP | 14+ | SOP |
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| ADM1184ARMZ | 3628 | AD | 15+ | MSOP10 |
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| LTC3421EUF | 3622 | LINEAR | 06+ | QFN |
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| MAX6012AEUR | 3612 | MAXIM | 15+ | SOT |
| AD8553ARMZ | 3612 | AD | 15+ | MSOP-10 |
| MX7523JCWE | 3593 | MXIC | 12+ | SOP |
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