LF398M integrated circuits ics , Monolithic Sample and Hold ic components
integrated circuit ic
,integrated circuit components
LF198/LF298/LF398, LF198A/LF398A
Monolithic Sample-and-Hold Circuits
General Description
The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 1010Ω allows high source impedances to be used without degrading accuracy. P-channel junction FET’s are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1 µF hold capacitor. The JFET’s have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages.
Features
- Operates from ±5V to ±18V supplies
- Less than 10 µs acquisition time
- TTL, PMOS, CMOS compatible logic input
- 0.5 mV typical hold step at Ch = 0.01 µF
- Low input offset
- 0.002% gain accuracy
- Low output noise in hold mode
- Input characteristics do not change during hold mode
- High supply rejection ratio in sample or hold
- Wide bandwidth
- Space qualified, JM38510
Logic inputs on the LF198 are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4V. The LF198 will operate from ±5V to ±18V supplies.
An “A” version is available with tightened electrical specifications.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage ±18V
Power Dissipation (Package Limitation) (Note 2) 500 mW
Operating Ambient Temperature Range LF198/LF198A −55˚C to +125˚C
LF298 −25˚C to +85˚C
LF398/LF398A 0˚C to +70˚C
Storage Temperature Range −65˚C to +150˚C
Input Voltage Equal to Supply Voltage
Logic To Logic Reference
Differential Voltage (Note 3) +7V, −30V
Output Short Circuit Duration Indefinite
Hold Capacitor Short Circuit Duration 10 sec
Lead Temperature (Note 4)
H package (Soldering, 10 sec.) 260˚C
N package (Soldering, 10 sec.) 260˚C
M package: Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
Thermal Resistance (θJA) (typicals)
H package 215˚C/W (Board mount in still air)
85˚C/W (Board mount in 400LF/min air flow)
N package 115˚C/W
M package 106˚C/W
θJC (H package, typical) 20˚C/W
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum junction temperature, TJMAX, for the LF198/LF198A is 150˚C; for the LF298, 115˚C; and for the LF398/LF398A, 100˚C.
Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the negative supply.
Note 4: See AN-450 “Surface Mounting Methods and their effects on Product Reliability” for other methods of soldering surface mount devices.
Typical Connection and Performance Curve
Functional Diagram
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