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74HCT374D,653 Linear And Digital Integrated Circuits , Computer Microchip

manufacturer:
Manufacturer
Description:
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width)
Category:
Integrated Circuit Chips
Price:
Negotiation
Payment Method:
T/T, Western Union,PayPal
Specifications
FEATURES:
• 3-state Non-inverting Outputs For Bus Oriented Applications
FEATURES2:
• 8-bit Positive, Edge-triggered Register
FEATURES3:
• Common 3-state Output Enable Input
FEATURES4:
• Independent Register And 3-state Buffer Operation
FEATURES5:
Output Capability: Bus Driver
FEATURES6:
• ICC Category: MSI
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Introduction

74HCT374D Linear And Digital Integrated Circuits , Computer Microchip

 

 

74HCT374D Octal D-type flip-flop; positive edge-trigger; 3-state

 

FEATURES

• 3-state non-inverting outputs for bus oriented applications

• 8-bit positive, edge-triggered register

• Common 3-state output enable input

• Independent register and 3-state buffer operation

• Output capability: bus driver

• ICC category: MSI

 

GENERAL DESCRIPTION

The 74HC/HCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

 

The 74HC/HCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The “374” is functionally identical to the “534”, but has non-inverting outputs

 

SYMBOL PARAMETER CONDITIONS
tPHL/ tPLH propagation delay CP to Qn CL = 15 pF; VCC = 5 V
fmax maximum clock frequency CL = 15 pF; VCC = 5 V
CI input capacitance  
CPD power dissipation capacitance per flip-flop notes 1 and 2

 

 

 

 

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