AM3352BZCZ30 AM3352BZCZD80 AM3354BZCZA100 AM3354BZCZD80 Microcontroller Integrated Circuit MPU Sitara ARM Cortex-A8 MPU
semiconductor integrated circuit
,pic microcontroller circuit
AM3352BZCZ30 AM3352BZCZD80 AM3354BZCZA100 AM3354BZCZD80 Microcontroller Integrated Circuit MPU Sitara ARM Cortex-A8 MPU
1 Features
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Up to 1-GHz SitaraTM ARM® Cortex®-A8 32‐Bit RISC Processor
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– NEONTM SIMD Coprocessor
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– 32KB of L1 Instruction and 32KB of Data Cache
With Single-Error Detection (Parity)
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– 256KB of L2 Cache With Error Correcting Code
(ECC)
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– 176KB of On-Chip Boot ROM
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– 64KB of Dedicated RAM
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– Emulation and Debug - JTAG
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– Interrupt Controller (up to 128 Interrupt
Requests)
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On-Chip Memory (Shared L3 RAM)
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– 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
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– Accessible to All Masters
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– Supports Retention for Fast Wakeup
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External Memory Interfaces (EMIF)
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– mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
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– mDDR: 200-MHz Clock (400-MHz Data Rate)
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– DDR2: 266-MHz Clock (532-MHz Data Rate)
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– DDR3: 400-MHz Clock (800-MHz Data Rate)
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– DDR3L: 400-MHz Clock (800-MHz Data
Rate)
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– 16-Bit Data Bus
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– 1GB of Total Addressable Space
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– Supports One x16 or Two x8 Memory Device
Configurations
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– General-Purpose Memory Controller (GPMC)
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– Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
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– Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
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– Uses Hamming Code to Support 1-Bit ECC
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– Error Locator Module (ELM)
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– Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
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– Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
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2 Applications
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Gaming Peripherals
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Home and Industrial Automation
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Consumer Medical Appliances
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Printers
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Smart Toll Systems
• Connected Vending Machines
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Weighing Scales
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Educational Consoles
• Advanced Toys
1.3 Description
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.
The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGXTM Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
Device Information
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PART NUMBER |
PACKAGE |
BODY SIZE |
|
AM3359ZCZ |
NFBGA (324) |
15.0 mm × 15.0 mm |
|
AM3358ZCZ |
NFBGA (324) |
15.0 mm × 15.0 mm |
|
AM3357ZCZ |
NFBGA (324) |
15.0 mm × 15.0 mm |
|
AM3356ZCZ, AM3356ZCE |
NFBGA (324), NFBGA (298) |
15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm |
|
AM3354ZCZ, AM3354ZCE |
NFBGA (324), NFBGA (298) |
15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm |
|
AM3352ZCZ, AM3352ZCE |
NFBGA (324), NFBGA (298) |
15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm |
|
AM3351ZCE |
NFBGA (298) |
13.0 mm × 13.0 mm |
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