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Home > products > Flash Memory IC Chip > DAC38J84EVM Data Conversion IC Development Tools DAC38J84 EVAL MO Data Conversion IC Development Tools DAC38J84 EVAL MOD

DAC38J84EVM Data Conversion IC Development Tools DAC38J84 EVAL MO Data Conversion IC Development Tools DAC38J84 EVAL MOD

manufacturer:
Manufacturer
Description:
DAC38J84 16 Bit 2.5G Samples Per Second Digital to Analog Converter (DAC) Evaluation Board
Category:
Flash Memory IC Chip
Price:
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Specifications
Subcategory:
Development Tools
Product Type:
Data Conversion IC Development Tools
Interface Type:
JESD204B
Brand:
Texas Instruments
Description/Function:
DAC38J84 Evaluation Moduleme][value]"Ti
Highlight:

semiconductor integrated circuit

,

pic microcontroller circuit

Introduction

DAC38J84EVM Data Conversion IC Development Tools DAC38J84 EVAL MO Data Conversion IC Development Tools DAC38J84 EVAL MOD
 
Functional Description
The DAC3XJ8XEVM is intended for evaluation of the DAC3XJ8X family of high-speed, JESD204B interface DACs. The digital input signal to the DAC is provided from the FMC connector (J16) on up to eight 12.5-Gbps SerDes lanes using the JESD204B interface standard. The FMC connector is also used for the SYNC signal required to establish the JESD204B link and both device clock and SYSREF signal for the FPGA.
The analog output of the DAC3XJ8X can be monitored on the installed SMA connectors labeled IOUTA through IOUTD for channels A through D, respectively. The analog outputs are transformer coupled and do not pass low frequency signals below approximately 10 MHz. The transformer converts the differential DAC output to a single-ended output for use with common laboratory equipment through wired SMA cable connections.
The clocks for the DAC and FPGA are distributed using the LMK04828 ultra low-noise clock jitter cleaner for JESD204B applications. The LMK04828 can be setup in a variety of configurations including clock distribution mode and dual-loop jitter cleaning mode. In clock distribution mode, the desired DAC output rate is provided to the CLKIN connector and the LMK04828 divides and distributes the device clocks and SYSREF signals. In dual-loop mode, the CLKIN connector can be used to provide a reference to the LMK04828, but the clocks are generated on board using the LMK04828 PLL and onboard 122.88 MHz VCXO.

Connector or Jumper Label

Reference Designator

Purpose

IOUTAP

J2

DAC Channel A transformer coupled output

IOUTBN

J8

DAC Channel B transformer coupled output

IOUTCP

J9

DAC Channel C transformer coupled output

IOUTDN

J11

DAC Channel D transformer coupled output

SPI_SELECTOR

JP3

Select SPI signal source. Short 1-2 for the FMC connector, 2-3 for USB.

1.8V_SEL

JP5

Select 1.8-V supply source for CPLD. Short 1-2 for board supply, 2-3 for USB power.

3.3V_SEL

JP6

Select 3.3-V supply source for CPLD. Short 1-2 for board supply, 2-3 for USB power.

CLKIN

J17

The clock input for LMK04828. The default setup provides clock to CLKIN1 but can be configured to provide a clock to OSCIN pins.

XO_PWR

JP2

Short jumper to provide power to onboard 122.88 MHz VCXO for PLL mode of the LMK04828. If not using the VCXO, disconnect power to prevent coupling into externally supplied clock.

TXENABLE

JP1

Controls the TXENABLE pin of the DAC3XJ8X. Short 1-2 to enable transmission.

SLEEP

JP4

Controls the SLEEP pin of the DAC3XJ8X. Short 1-2 to put DAC to sleep.

FMC_CONNECTOR

J16

Connection to TSW14J56 or FPGA development board

USB

J14

USB cable port

+5V_IN

J23

5-V power supply barrel jack

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