SN65DSI83ZQER UART Interface IC LVDS Interface IC MIPI DSI Bridge to FlatLink LVDS
uart multiplexer ic
,uart level shifter ic
SN65DSI83ZQER UART Interface IC LVDS Interface IC MIPI DSI Bridge to FlatLink LVDS
1 Features
- Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
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Single Channel DSI Receiver Configurable for 1, 2, 3, or 4 D-PHY Data Lanes Per Channel Operating up to 1 Gbps/Lane
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Supports 18 bpp and 24 bpp DSI Video Packets With RGB666 and RGB888 Formats
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Max Resolution up to 60 fps WUXGA
1920 × 1200 at 18 bpp and 24 bpp Color With Reduced Blanking. Suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp -
FlatLinkTM Output for Single-Link LVDS
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Supports Single Channel DSI to Single-Link LVDS Operating Mode
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LVDS Output Clock Range of 25 MHz to 154 MHz
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LVDS Pixel Clock May be Sourced from Free- Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
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1.8-V Main VCC Power Supply
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Low Power Features Include Shutdown Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
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LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
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ESD Rating ±2 kV (HBM)
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Packaged in 64-pin 5-mm × 5-mm BGA MICROSTAR JUNIOR (ZQE)
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Temperature Range: –40°C to 85°C
2 Applications
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Tablet PC, Notebook PC, Netbooks
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Mobile Internet Devices
3 Description
The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front- end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.
The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra- low power state (ULPS) support.
The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm BGA MICROSTAR JUNIOR at 0.5-mm pitch package, and operates across a temperature range from –40oC to 85oC.
Device Information
|
PART NUMBER |
PACKAGE |
BODY SIZE |
|
SN65DSI83 |
BGA MICROSTAR JUNIOR (64) |
5.00 mm × 5.00 mm |
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