EP3C40F324C8N EP3C40F484C8 EP3C40F484C8N EP3C40F484I7N EP3C40F780C6N EP3C40Q240C8N Programmable Logic ICS Field Program
logic integrated circuits
,programmable logic array ic
EP3C40F324C8N EP3C40F484C8 EP3C40F484C8N EP3C40F484I7N EP3C40F780C6N EP3C40Q240C8N Programmable Logic ICS Field Program
Lowest Power FPGAs
- Lowest power consumption with TSMC low-power process technology and Altera® power-aware design flow
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Low-power operation offers the following benefits:
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Extended battery life for portable and handheld applications
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Reduced or eliminated cooling system costs
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Operation in thermally-challenged environments
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Hot-socketing operation support
Design Security Feature
Cyclone III LS devices offer the following design security features:
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Configuration security using advanced encryption standard (AES) with 256-bit volatile key
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Routing architecture optimized for design separation flow with the Quartus® II software
■ Design separation flow achieves both physical and functional isolation between design partitions
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Ability to disable external JTAG port
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Error Detection (ED) Cycle Indicator to core
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Provides a pass or fail indicator at every ED cycle
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Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
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Ability to perform zeroization to clear contents of the FPGA logic, CRAM, embedded memory, and AES key
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Internal oscillator enables system monitor and health check capabilities
Increased System Integration
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High memory-to-logic and multiplier-to-logic ratio
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High I/O count, low-and mid-range density devices for user I/O constrained
applications
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Adjustable I/O slew rates to improve signal integrity
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Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
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Supports the multi-value on-chip termination (OCT) calibration feature to eliminate variations over process, voltage, and temperature (PVT)
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Four phase-locked loops (PLLs) per device provide robust clock management and synthesis for device clock management, external system clock management, and I/O interfaces
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Five outputs per PLL
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Cascadable to save I/Os, ease PCB routing, and reduce jitter
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Dynamically reconfigurable to change phase shift, frequency multiplication or division, or both, and input frequency in the system without reconfiguring the device
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Remote system upgrade without the aid of an external controller
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Dedicated cyclical redundancy code checker circuitry to detect single-event upset
(SEU) issues
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Nios® II embedded processor for Cyclone III device family, offering low cost and custom-fit embedded processing solutions
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