EP2S180F1020C3N Programmable Logic ICS Field Programmable Gate Array FPGA - Stratix II 8970 LABs 742 IOs
logic integrated circuits
,programmable logic array ic
EP2S180F1020C3N Programmable Logic ICS Field Programmable Gate Array FPGA - Stratix II 8970 LABs 742 IOs
Features
-
15,600 to 179,400 equivalent LEs; see Table 1–1
-
New and innovative adaptive logic module (ALM), the basic
building block of the Stratix II architecture, maximizes performance
and resource usage efficiency
-
Up to 9,383,040 RAM bits (1,172,880 bytes) available without
reducing logic resources
-
TriMatrix memory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers
-
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
-
Up to 16 global clocks with 24 clocking resources per device region
-
Clock control blocks support dynamic clock network enable/disable,
which allows clock networks to power down to reduce power
consumption in user mode
-
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switch- over, real-time PLL reconfiguration, and advanced multiplication and phase shifting
-
Support for numerous single-ended and differential I/O standards
-
High-speed differential I/O support with DPA circuitry for 1-Gbps
performance
-
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransportTM technology, and SFI-4
-
Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
-
Support for multiple intellectual property megafunctions from
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
-
Support for design security using configuration bitstream
encryption
-
Support for remote configuration updates
|
Table 1–1. Stratix II FPGA Family Features |
||||||
|
Feature |
EP2S15 |
EP2S30 |
EP2S60 |
EP2S90 |
EP2S130 |
EP2S180 |
|
ALMs |
6,240 |
13,552 |
24,176 |
36,384 |
53,016 |
71,760 |
|
Adaptive look-up tables (ALUTs) (1) |
12,480 |
27,104 |
48,352 |
72,768 |
106,032 |
143,520 |
|
Equivalent LEs (2) |
15,600 |
33,880 |
60,440 |
90,960 |
132,540 |
179,400 |
|
M512 RAM blocks |
104 |
202 |
329 |
488 |
699 |
930 |
|
M4K RAM blocks |
78 |
144 |
255 |
408 |
609 |
768 |
|
M-RAM blocks |
0 |
1 |
2 |
4 |
6 |
9 |
|
Total RAM bits |
419,328 |
1,369,728 |
2,544,192 |
4,520,488 |
6,747,840 |
9,383,040 |
|
DSP blocks |
12 |
16 |
36 |
48 |
63 |
96 |
|
18-bit × 18-bit multipliers (3) |
48 |
64 |
144 |
192 |
252 |
384 |
|
Enhanced PLLs |
2 |
2 |
4 |
4 |
4 |
4 |
|
Fast PLLs |
4 |
4 |
8 |
8 |
8 |
8 |
|
Maximum user I/O pins |
366 |
500 |
718 |
902 |
1,126 |
1,170 |
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