TLC555IDR Clock Timer ICS Timers & Support Products CMOS
timer ic chip
,time delay ic chip
TLC555IDR Clock Timer ICS Timers & Support Products CMOS
1 Features
- Very Low Power Consumption:
– 1mWTypicalatVDD =5V
Capable of Operation in Astable Mode
CMOS Output Capable of Swinging Rail to Rail
High Output Current Capability
– Sink: 100 mA Typical
– Source: 10 mA Typical
Output Fully Compatible With CMOS, TTL, and MOS
Low Supply Current Reduces Spikes During Output Transitions
Single-Supply Operation From 2 V to 15 V
Functionally Interchangeable With the NE555; Has Same Pinout
ESD Protection Exceeds 2000 V Per MIL-STD- 883C, Method 3015.2
Available in Q-Temp Automotive
– High-Reliability Automotive Applications
– Configuration Control and Print Support
– Qualification to Automotive Standards
2 Applications
Precision Timing
Pulse Generation
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation
Linear Ramp Generator
3 Description
The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOSTM process. The timer is fully compatible with CMOS, TTL, and MOS logic, and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.
Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip- flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.
Device Information
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
TLC555C | SOIC (8) | 4.9 mm × 3.91 mm |
PDIP (8) | 9.81 mm × 6.38 mm | |
SOP (8) | 6.20 mm × 5.30 mm | |
TSSOP (14) | 5.00 mm × 4.40 mm | |
TLC555I | SOIC (8) | 4.90 mm × 3.91 mm |
PDIP (8) | 9.81 mm × 6.38 mm | |
TLC555M | LCCC (20) | 8.89 mm × 8.89 mm |
CDIP (8) | 9.60 mm × 6.67 mm | |
TLC555Q | SOIC (8) | 4.90 mm × 3.91 mm |
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