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Home > products > Flash Memory IC Chip > CD74HCT541M96 Programmable Logic ICS Buffers & Line Drivers Tri-St N-Invrt Octal

CD74HCT541M96 Programmable Logic ICS Buffers & Line Drivers Tri-St N-Invrt Octal

manufacturer:
Manufacturer
Description:
Buffer, Non-Inverting 1 Element 8 Bit per Element 3-State Output 20-SOIC
Category:
Flash Memory IC Chip
Price:
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Payment Method:
Paypal, Western Union, TT
Specifications
Height:
2.35 Mm
Logic Type:
CMOS
Number Of Channels:
8
Supply Current - Max:
8 UA
High Level Output Current:
- 6 MA
Input Signal Type:
Single-Ended
Highlight:

logic integrated circuits

,

programmable logic array ic

Introduction

CD74HCT541M96 Programmable Logic ICS Buffers & Line Drivers Tri-St N-Invrt Octal

 

Features

  • ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

  • ’HC541,’HCT541...................... Non-Inverting

  • Buffered Inputs

  • Three-State Outputs

  • Bus Line Driving Capability

  • Typical Propagation Delay = 9ns at VCC = 5V, CL = 15pF, TA = 25oC

  • Fanout (Over Temperature Range)

    • - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

    • - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

  • Wide Operating Temperature Range . . . -55oC to 125oC

  • Balanced Propagation Delay and Transition Times

  • Significant Power Reduction Compared to LSTTL Logic ICs

  • HC Types

    • - 2V to 6V Operation

    • - High Noise Immunity: NIL = 30%, NIH = 30% of VCC

      at VCC = 5V

  • HCT Types

    • - 4.5V to 5.5V Operation

    • - Direct LSTTL Input Logic Compatibility,

      VIL= 0.8V (Max), VIH = 2V (Min)

    • - CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

 

Description

The ’HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non- Inverting Octal Buffers and Line Drivers with Three-State Out- puts that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high imped- ance state. For data output OE1 and OE2 both must be LOW.

Ordering Information

PART NUMBER

TEMP. RANGE (oC)

PACKAGE

CD54HC540F3A

-55 to 125

20 Ld CERDIP

CD54HC541F3A

-55 to 125

20 Ld CERDIP

CD54HCT541F3A

-55 to 125

20 Ld CERDIP

CD74HC540E

-55 to 125

20 Ld PDIP

CD74HC540M

-55 to 125

20 Ld SOIC

CD74HC540M96

-55 to 125

20 Ld SOIC

CD74HC541E

-55 to 125

20 Ld PDIP

CD74HC541M

-55 to 125

20 Ld SOIC

CD74HC541M96

-55 to 125

20 Ld SOIC

CD74HC541PW

-55 to 125

20 Ld TSSOP

CD74HC541PWR

-55 to 125

20 Ld TSSOP

CD74HCT540E

-55 to 125

20 Ld PDIP

CD74HCT540M

-55 to 125

20 Ld SOIC

CD74HCT540M96

-55 to 125

20 Ld SOIC

CD74HCT541E

-55 to 125

20 Ld PDIP

CD74HCT541M

-55 to 125

20 Ld SOIC

CD74HCT541M96

-55 to 125

20 Ld SOIC

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