ADS4246IRGCR Electronic IC Chips Dual-Channel, 14-/12-Bit Ultralow-Power ADC
electronic integrated circuit
,linear integrated circuits
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
Dual-Channel, 14-/12-Bit, 160/125/65MSPS Ultralow-Power ADC
FEATURES
• Ultralow Power with Single 1.8V Supply, CMOS Output:
– 183mW total power at 65MSPS
– 277mW total power at 125MSPS
– 332mW total power at 160MSPS
• High Dynamic Performance:
– 88dBc SFDR at 170MHz
– 71.4dBFS SNR at 170MHz
• Crosstalk: > 90dB at 185MHz
• Programmable Gain up to 6dB for SNR/SFDR Trade-off
• DC Offset Correction
• Output Interface Options:
– 1.8V parallel CMOS interface
– Double data rate (DDR) LVDS with programmable swing:
– Standard swing: 350mV
– Low swing: 200mV
• Supports Low Input Clock Amplitude Down to 200mVPP
• Package: QFN-64 (9mm × 9mm)
APPLICATIONS
• Wireless Communications Infrastructure
• Software Defined Radio
• Power Amplifier Linearization
DESCRIPTION
The ADS424x/422x are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit/12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.
The ADS424x/422x have gain options that can be used to improve SFDR performance at lower full-scale input ranges. These devices include a dc offset correction loop that can be used to cancel the ADC offset. Both DDR (double data rate) LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD™ package.
The devices include internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. All devices are specified over the industrial temperature range (–40°C to +85°C).
ABSOLUTE MAXIMUM RATINGS(1)
| ADS424x/422x | UNIT | |||
| MIN | MAX | |||
| Supply voltage range, AVDD | –0.3 | 2.1 | V | |
| Supply voltage range, DRVDD | –0.3 | 2.1 | V | |
| Voltage between AGND and DRGND | –0.3 | 0.3 | V | |
| Voltage between AVDD to DRVDD (when AVDD leads DRVDD) | –2.4 | 2.4 | V | |
| Voltage between DRVDD to AVDD (when DRVDD leads AVDD) | –2.4 | 2.4 | V | |
| Voltage applied to input pins | INP_A, INM_A, INP_B, INM_B | –0.3 |
Minimum (1.9, AVDD + 0.3) |
V |
| CLKP, CLKM(2) | –0.3 | AVDD + 0.3 | ||
| RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3 | –0.3 | 3.9 | ||
| Operating free-air temperature range, TA | –40 | +85 | °C | |
| Operating junction temperature range, TJ | +125 | °C | ||
| Storage temperature range, Tstg | –65 | +150 | °C | |
| ESD rating | Human body model (HBM) | 2 | kV | |
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on.
Stock Offer (Hot Sell)
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