Quad Monolithic PCM Codec / Filter Electronic IC Chips TP3094V/NOPB , four voice channels

Quad Monolithic PCM Codec / Filter Electronic IC Chips TP3094 , four voice channels

General Description

The TP3094 is a monolithic PCM Codec and Filter device implemented using a digital signal processing architecture. It provides four voice channels, combining transmit bandpass and receive low pass channel filters with companding Alaw or m-law PCM encoders and decoders. The device is fabricated using National’s advanced CMOS process.

The device includes anti-aliasing filters and sigma-delta converters dedicated to each channel, and by a common signal processing unit which performs all the remaining filtering and processing for the four channels.

The TP3094 includes a flexible PCM digital interface, which allows the device to be connected to PCM busses of different formats. It can also be connected with other TP3094 devices in a cascade fashion, for a system with up to 128 POTS interfaces (when a 2.048MHz PCM bus is used).

Features

• Handles four voice channels

• Complete Codec and Filter system including: - Transmit and receive channel filters - A-law or m-law          companding encoder/decoder

• Power down mode for low power consumption

• Compatible to standard time division multiplexed PCM bus - 8 bit mode, frame signal from external reference -    32 bit mode, internal TSA, with consecutive TS

• Up to 128 channels (32 devices) can be cascaded

• Programmable functions (common for all 4 channels): - A-law or m-law - Single MCLK clock,automatically  selectable from 8.192MHz, 4.096MHz, 2.048MHz and 1.536/1.544MHz - Digital and Analog loopback test modes

• Designed for CCITT and LSSGR applications

• Single +5V power supply

• 44 lead PLCC surface mount package

• Maximize line card circuit density

• Use in Central Office, Loop Carrier, and PBX equipment subscriber line and trunk cards

• Wide operating temperature range -40°C to 85°C

Pin Descriptions

MCLK (input) Master and PCM bit clock input. Must be either 1.536MHz/1.544MHz, 2.048MHz, 4.096MHz or 8.192MHz. Its value is automatically detected internally on power up with the valid frame sync input.

AVCC0, AVCC1

Positive supply pins for the analog circuitry. AVCC0 is for channel 0 and channel 1. AVCC1 is for channel 2 and channel 3.

AVCC0=AVCC1=+5V ±5%. These two pins should be connected together outside the device.

AGND0, AGND1

Analog ground. All analog signals are referenced to AGND0 and AGND1. AGND0 is the analog ground for channel 0 and channel 1. AGND1 is the analog ground for channel 2 and channel 3. These two pins should be connected together outside the device.

DVCC

Positive supply for the digital circuitry.

DVCC=+5V ±5%.

DGND

Digital ground. All logic signals are referenced to DGND. This ground has to be connected to the ground of other digital devices at board level.

Analog ports

VXI0-, VXI1-, VXI2-, VXI3- (inputs)

Inverting analog inputs of the transmit input amplifiers of channels 0-3. They are referenced to an internal reference voltage of about 2.4V.

GXO0, GXO1, GXO2, GXO3 (outputs)

Outputs of the transmit input amplifiers of channels 0-3. They are referenced to an internal reference voltage of about 2.4V

VRO0, VRO1, VRO2, VRO3 (ouputs) Analog outputs of the receive amplifiers for channels 0-3. They are referenced to an internal reference voltage of about 2.4V

PCM Port

DX (ouput)

Transmit PCM data output. Serial PCM data is shifted out on the rising edge of MCLK during the assigned transmit time-slot. Tristated when the assigned transmit time-slot is not active.

TSx (ouput)

Open drain output that pulses low during the assigned transmit time-slots (for all four channels).

DR (input)

Receive PCM data input. Serial PCM data is shifted into the device on the falling edge of MCLK during the assigned receive time-slot.

FSX0, FSR0 (inputs)

Transmit and Receive Frame synchronization inputs for channel 0. They identify the beginning of a new frame in the transmit and receive direction. They are 8 KHz logic signals, and must be synchronous to MCLK. Short Frame Sync and Long Frame Sync are both supported. In 32-bit mode these signals constitute the 8kHz reference for all channels. Only Short Frame Sync is supported in 32-bit mode.

FSX1, FSR1 (inputs/outputs)

Transmit and Receive Frame synchronization inputs for channel 1.

In 32-bit mode these pins become outputs and generate a frame sync signal with the last bit of the 32-bit stream, in order to allow to cascade another TP3094 in 32-bit mode. FSX1 is the Transmit Frame output and FSR1 is the Receive Frame output.

FSX2,FSX3, FSR2,FSR3 (inputs)

Transmit and Receive Frame synchronization inputs for channel 2 and 3. These pins are recommended to be connected to analog ground when in 32-bit mode.

A/u LAW select (input)

A/u law select. Through this pin either A-law (+5V) or u-law (0V) is selected.

PDN0-3 (input)

Power Down control signals. Each channel has a dedicated Power Down input. When active high, these pins set the low power mode, shutting down most of the circuitry dedicated to it and reducing the power consumption. The relative analog outputs VROi and GXOi, and the digital output DX are put in high impedance.

TST (input)

Test Modes Enable. When active (HIGH), together with the PDNi pins selects one of the available test modes (see the text for a full description of these modes).

PCMMode (input)

PCM Mode selection. When this signal is LOW (0V), the 8 bit mode is selected and each channel expects its individual transmit and receive frame signal. When it is HIGH, the 32 bit mode is selected; in this mode FSX0 and FSR0 are used as framing signals and the TS are allocated consecutively from these frames, starting from Ch0 to Ch3. In this mode FSX1 and FSR1 become outputs and produce 1 bit long frame signals with the last bit of the 32 bit stream. These Frame signals can be used to cascade another device in 32 bit mode.

NF

Noise Filter Pin. For optimal noise rejection a 100nF capacitor must be connected between this pin and the analog ground AGND0.

PT1, PT2, PT3, PT4 (inputs)

These pins are used by National for internal manufacturing test. They must be connected to digital ground for normal device operation.

NC

All NC pins must be connected to nearest analog ground, to reduce the device noise sensitivity.