Silicon Circuit Board Chips DP83848CVVX/NOPB Ethernet Physical Layer Transceiver
digital integrated circuits
,linear integrated circuits
Silicon Circuit Board Chips DP83848C Ethernet Physical Layer Transceiver
DP83848C PHYTER Commercial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
General Description The DP83848C is a robust fully featured 10/100 single port Physical Layer device offering low power consumption, including several intelligent power down states. These low power modes increase overall product reliability due to decreased power dissipation. Supporting multiple intelligent power modes allows the application to use the absolute minimum amount of power needed for operation. The DP83848C includes a 25MHz clock out. This means that the application can be designed with a minimum of external parts, which in turn results in the lowest possible total cost of the solution. The DP83848C easily interfaces to twisted pair media via an external transformer. Both MII and RMII are supported ensuring ease and flexibility of design. The DP83848C features integrated sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensures compatibility and interoperability with all other standards based Ethernet solutions. The DP83848C is offered in a small form factor (48 pin LQFP) so that a minimum of board space is needed.
Features
• Low-power 3.3V, 0.18µm CMOS technology
• Low power consumption < 270mW Typical
• 3.3V MAC Interface
• Auto-MDIX for 10/100 Mb/s
• Energy Detection Mode
• 25 MHz clock out
• SNI Interface (configurable)
• RMII Rev. 1.2 Interface (configurable)
• MII Serial Management Interface (MDC and MDIO)
• IEEE 802.3u MII
• IEEE 802.3u Auto-Negotiation and Parallel Detection
• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
• IEEE 802.3u PCS, 100BASE-TX transceivers and filters
• Integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
• Error-free Operation up to 137 meters
• Programmable LED support Link, 10 /100 Mb/s Mode, Activity, and Collision Detect
• Single register access for complete PHY status
• 10/100 Mb/s packet BIST (Built in Self Test)
• 48-pin LQFP package (7mm) x (7mm)
Special Connections
| Signal Name | Type | Pin # | Description |
| RBIAS | I | 24 | Bias Resistor Connection. A 4.87 kΩ 1% resistor should be connected from RBIAS to GND. |
| PFBOUT | O | 23 | Power Feedback Output. Parallel caps, 10µ F (Tantalum preferred) and 0.1µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See Section 5.4 for proper placement pin. |
| PFBIN1 PFBIN2 | I |
18 37 |
Power Feedback Input. These pins are fed with power from PFBOUT pin. A small capacitor of 0.1µF should be connected close to each pin. Note: Do not supply power to these pins other than from PFBOUT. |
| RESERVED | I/O | 8,9,10,11,12 | RESERVED: These pins must be left unconnected. |
| RESERVED | I/O | 20,21 | RESERVED: These pins must be pulled-up through 2.2 kΩ resistors to AVDD33 supply. |
Power Supply Pins
| Signal Name | PIN# | Description |
| IOVDD33 | 32,48 | I/O 3.3V Supply |
| IOGND | 35,47 | I/O Ground |
| DGND | 36 | Digital Ground |
| AVDD33 | 22 | Analog 3.3V Supply |
| AGND | 15,19 | Analog Ground |
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