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Home > products > Integrated Circuit Chips > NPN Power Mosfet Transistor Double Transistors Output Latches 3-State 74AHCT595PW,118

NPN Power Mosfet Transistor Double Transistors Output Latches 3-State 74AHCT595PW,118

manufacturer:
Manufacturer
Description:
Shift Shift Register 1 Element 8 Bit 16-TSSOP
Category:
Integrated Circuit Chips
Price:
negotiation
Payment Method:
T/T, Western Union,PayPal
Specifications
Input Levels 1:
The 74AHC595 Operates With CMOS Input Levels
Input Levels 2:
The 74AHCT595 Operates With TTL Input Levels
ESD Protection 1:
HBM JESD22-A114E Exceeds 2000 V
ESD Protection 2:
MM JESD22-A115-A Exceeds 200 V
ESD Protection 3:
CDM JESD22-C101C Exceeds 1000 V
Feature 6:
Specified From −40 °C To +85 °C And From −40 °C To +125 °C
Highlight:

power mosfet ic

,

multi emitter transistor

Introduction

1. General description

 

                        The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin

                        compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with

                        JEDEC standard No. 7A.

 

                        The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and

                        3-state outputs. The registers have separate clocks.

 

                        Data is shifted on the positive-going transitions of the shift register clock input (SHCP).

                        The data in each register is transferred to the storage register on a positive-going

                        transition of the storage register clock input (STCP). If both clocks are connected together,

                        the shift register will always be one clock pulse ahead of the storage register.

 

                        The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.

                        It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The

                        storage register has 8 parallel 3-state bus driver outputs. Data in the storage register

                        appears at the output whenever the output enable input (OE) is LOW

 

2. Features

 

                        ■ Balanced propagation delays

                        ■ All inputs have Schmitt-trigger action

                        ■ Inputs accept voltages higher than VCC

                        ■ Input levels:

                            ◆ The 74AHC595 operates with CMOS input levels

                            ◆ The 74AHCT595 operates with TTL input levels

                        ■ ESD protection:

                            ◆ HBM JESD22-A114E exceeds 2000 V

                            ◆ MM JESD22-A115-A exceeds 200 V

                            ◆ CDM JESD22-C101C exceeds 1000 V

                        ■ Multiple package options

                        ■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

 

3. Applications

 

                        ■ Serial-to-parallel data conversion

                        ■ Remote control holding register

 

4. Ordering information

 

Type number Package
Temperature range       Name  Description     Version
74AHC595        
74AHC595D

−40 °C to +125 °C               

                                                                                                                           

SO16

plastic small outline package;16 leads; body

width 3.9 mm

SOT109-1
74AHC595PW

−40 °C to +125 °C    

TSSOP16 plastic thin shrink small outline package;16 leads; body width 4.4 mm SOT403-1
74AHC595BQ

−40 °C to +125 °C     

DHVQFN16

plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;16 terminals; body 2.5 × 3.5 ×0.85mm 

 

SOT763-1

 

5. Functional diagram

 

 

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