Electrical Circuit Board Chips High Speed 75ALS180 SN75ALS180DR
circuit board ic
,electronic chip board
Electrical Circuit Board Chips High Speed 75ALS180 SN75ALS180
75ALS180 SN75ALS180 DIFFERENTIAL DRIVER AND RECEIVER PAIRS
FEATURES
Meet or Exceed the Requirements of TIA/EIA-422-B, TIA/EIA-485-A† and ITU Recommendation V.11
High-Speed Advanced Low-Power Schottky Circuitry
Designed for 25-Mbaud Operation in Both Serial and Parallel Applications
Low Skew Between Devices . . . 6 ns Max
Low Supply-Current Requirements . . . 30 mA Max
Individual Driver and Receiver I/O Pins With Dual VCC and Dual GND
Wide Positive and Negative Input/Output Bus Voltage Ranges
Driver Output Capacity . . . ±60 mA
Thermal Shutdown Protection
Driver Positive- and Negative-Current Limiting
Receiver Input Impedance . . . 12 kΩ Min Receiver Input Sensitivity . . . ±200 mV Max
Receiver Input Hysteresis . . . 60 mV Typ
Operate From a Single 5-V Supply
Glitch-Free Power-Up and Power-Down Protection
description/ordering information
The SN65ALS180 and SN75ALS180 differential driver and receiver pairs are integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. They are designed for balanced transmission lines and meet TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendation V.11.
The SN65ALS180 and SN75ALS180 combine a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected to separate terminals for greater flexibility and are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications.
| PARAMETER | TEST CONDITIONS | MIN TYP‡ MAX | UNIT |
| td(OD) Differential output delay time | RL = 54 Ω, CL = 50 pF, See Figure 3 | 3 8 13 | ns |
| Pulse skew (td(ODH) – td(ODL)) | RL = 54 Ω, CL = 50 pF, See Figure 3 | 1 6 | ns |
| tt(OD) Differential output transition time | RL = 54 Ω, CL = 50 pF, See Figure 3 | 3 8 13 | ns |
| tPZH Output enable time to high level | RL = 110 Ω, See Figure 4 | 23 50 | ns |
| tPZL Output enable time to low level | RL = 110 Ω, See Figure 5 | 19 24 | ns |
| tPHZ Output disable time from high level | RL = 110 Ω, See Figure 4 | 8 13 | ns |
| tPLZ Output disable time from low level | RL = 110 Ω, See Figure 5 | 8 13 | ns |
‡ All typical values are at VCC = 5 V and TA = 25°C
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