M24512-WMN6TP Programmable Circuit Board , Programming IC Chips
programming ic chips
,programmable audio chip
M24512 - WMN6TP Programmable Circuit Board , Programming IC Chips
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| NDF06N60ZG | 8221 | ON | 14+ | TO-220 |
| NDP6020P | 5891 | FAIRCHILD | 13+ | TO-220 |
| NDS355AN | 137000 | FAIRCHILD | 15+ | SOT-23 |
| NDT014L | 96000 | FAIRCHILD | 04+ | SOT-223 |
| NE5550979A-T1-A | 6042 | RENESAS | 16+ | 79NA |
| NE555DR | 40000 | TI | 16+ | SOP-8 |
| NE555PWR | 78000 | TI | 14+ | TSSOP-8 |
| NE555PWR | 51000 | TI | 15+ | TSSOP-8 |
| NE556N | 8450 | TI | 15+ | DIP-14 |
| NFA21SL506X1A48L | 64000 | MURATA | 13+ | SMD |
| NFL21SP106X1C3D | 17325 | MURATA | 15+ | SMD |
| NFM21CC471R1H3D | 33000 | MURATA | 16+ | SMD |
| NFM3DPC223R1H3L | 61000 | MURATA | 13+ | SMD |
| NH82801GB-SL8FX | 1822 | INTEL | 15+ | BGA |
| NJM064M | 6020 | JRC | 16+ | SOP-14 |
| NJM1300D | 6703 | JRC | 16+ | DIP-16 |
M24512-W M24512-R
M24256-BW M24256-BR
512 Kbit and 256 Kbit Serial I²C bus EEPROM with three Chip Enable lines
Feature summary
■ Two-wire I2C Serial interface supports 400 kHz Protocol
■ Supply voltage ranges:
■ 1.8 V to 5.5 V (M24xxx-R)
■ 2.5 V to 5.5 V (M24xxx-W)
■ Write Control Input
■ Byte and Page Write
■ Random and sequential read modes
■ Self-timed programming cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Protection
■ More than 1,000,000 Write cycles
■ More than 40-year data retention
■ Packages – ECOPACK® (RoHS compliant)
Summary description
The M24512-W, M24512-R, M24256-BW and M24256-BR devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 64 Kb × 8 bits and 32 Kb × 8 bits, respectively.
I 2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I 2C bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as described in Table 2), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS compliant.
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